Prior art circuits are available for converting an incoming time varying signal to DC levels or to an intermediate frequency. It is known to provide the desired conversion by multiplication of the amplitude values of the incoming signal.
A frequently used and well known circuit for this purpose is known as a transconductance multiplier, utilizing bipolar integrated circuits. However, matching difficulties and inherent nonlinearity problems make such circuits unsuitable for implementation using MOS devices. An alternate arrangement used in MOS circuitry is capable of multiplying an incoming signal by a square wave. In such an arrangement, the incoming signal is multiplied by a local oscillator signal, utilizing a switching arrangement for passing the incoming signal during one half of the period of the local oscillator. During the second half of the local oscillator period the switching arrangement passes the inverted form of the input signal.
The square wave by which the incoming signal is multiplied thus has a frequency determined by the frequency of the local oscillator. However, square waves, as well as signals multiplied thereby, are found to have many odd harmonic components. Thus, if an input signal has a frequency component at or near any of the odd harmonics, multiplication by the square wave results in translation of that component to a lower frequency, or to a DC level, which cannot be separated from a required signal which originally was near or at the square wave fundamental frequency. Accordingly, a difficulty with the prior art is a requirement of prefiltering the input signal to remove the above identified components. Such prefiltering frequently requires high-order filters.
Still a further technique known in the art utilizes a multiplying digital-to-analog converter (DAC). In such structures, an incoming signal is applied to a reference input of the converter and a digital conversion coefficient is changed at a rhythm which is some multiple of the desired local oscillator frequency. However, the coefficients thus used are portions of a binary sequence, rather than analog numbers. Thus, any multiplication by a DAC results in increased harmonic content and unwanted intermodulation products, which reduces the fidelity of the output signal as a representation of multiplication of the input signal by a sinusoid.
Digital filter circuits are known wherein capacitances are switched in and out of a circuit in order to change the filter characteristic thereof to eliminate a parasitic capacitance problem. However, when MOS switching devices are used in demodulators, the prior art typically utilizes the same merely for sampling a signal and for providing the sample for storage on a capacitor. Thus, it is known to charge and discharge holding capacitors utilizing MOS switching devices.
The prior art also teaches attenuation of a particular mark frequency applied to a demodulator by utilization of MOS devices to switch capacitances in to and out of the circuit.
However, the prior art does not teach or disclose an efficient manner or apparatus for multiplying time varying signals by analog coefficients, which represent sinusoidal coefficients, utilizing efficient switching techniques. The prior art more particularly is deficient in providing an arrangement for multiplying a sequence of samples of a first signal by a corresponding sequence of analog multiplicands representing hypothetical coefficients or samples of a second time varying signal in order to obtain a product signal, a heterodyne signal, or to generate an arbitrary time function, such as a sinusoidal signal.